[HELP] Dead TV box, what do you make out of this log (Tanix TX3 S905X3 4/64)

S905D, S905, S8xx Series and other box users can discuss here :)
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masteripper
Posts: 3
Joined: Wed Jun 23, 2021 8:33 am
Has thanked: 1 time

#1

Short Story , dead TV box...no Leds,Lights,output...nothing...but serial console works

Any idea of what is wrong
(Is UART flashing a good option...has someone done it successfully ?)

Code: Select all

=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2020.10.06 13:20:30 =~=~=~=~=~=~=~=~=~=~=~=
SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:0;READ:0;0.0;CHK:0;
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0001 - pwm id 0x00
bl2_stage_init 0xc0
bl2_stage_init 0x02

L0:00000000
L1:00000703
L2:00008067
L3:15000020
S1:00000000
B2:20282000
B1:a0f83180

TE: 135603

BL2 Built : 14:57:11, Sep  1 2020. g12a g3c95fed - gongwei.chen@droid11-sz

Board ID = 1
Set cpu clk to 24M
Set clk81 to 24M
Use GP1_pll as DSU clk.
DSU clk: 1200 Mhz
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
board id: 1
Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
PIEI prepare done
00000000
emmc switch 1 ok
ddr saved addr:00016000
Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
00000000
emmc switch 0 ok
fastboot data verify
result: 255
Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
DDR4 probe

LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep  1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
ddr clk to 1320MHz

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 3. Board id: 255. Force loop cfg
DDR3 probe
ddr clk to 648MHz

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 4. Board id: 255. Force loop cfg
DDR3 probe
ddr clk to 648MHz

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 5. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 912MHz

dmc_version 0001
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : End of initialization
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 6. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 912MHz

dmc_version 0001
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : End of initialization
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 7. Board id: 0. not match..skip..
Cfg max: 12, cur: 8. Board id: 0. not match..skip..
Cfg max: 12, cur: 9. Board id: 0. not match..skip..
Cfg max: 12, cur: 10. Board id: 0. not match..skip..
Cfg max: 12, cur: 11. Board id: 0. not match..skip..
Cfg max: 12, cur: 12. Bo SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:0;READ:0;0.0;CHK:0;
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0001 - pwm id 0x00
bl2_stage_init 0xc0
bl2_stage_init 0x02

L0:00000000
L1:00000703
L2:00008067
L3:15000020
S1:00000000
B2:20282000
B1:a0f83180

TE: 130693

BL2 Built : 14:57:11, Sep  1 2020. g12a g3c95fed - gongwei.chen@droid11-sz

Board ID = 1
Set cpu clk to 24M
Set clk81 to 24M
Use GP1_pll as DSU clk.
DSU clk: 1200 Mhz
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
board id: 1
Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
PIEI prepare done
00000000
emmc switch 1 ok
ddr saved addr:00016000
Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
00000000
emmc switch 0 ok
fastboot data verify
result: 255
Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
DDR4 probe

LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep  1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
ddr clk to 1320MHz

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 3. Board id: 255. Force loop cfg
DDR3 probe
ddr clk to 648MHz

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 4. Board id: 255. Force loop cfg
DDR3 probe
ddr clk to 648MHz

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 5. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 912MHz

dmc_version 0001
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : End of initialization
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 6. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 912MHz

dmc_version 0001
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : End of initialization
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 7. Board id: 0. not match..skip..
Cfg max: 12, cur: 8. Board id: 0. not match..skip..
Cfg max: 12, cur: 9. Board id: 0. not match..skip..
Cfg max: 12, cur: 10. Board id: 0. not match..skip..
Cfg max: 12, cur: 11. Board id: 0. not match..skip..
Cfg max: 12, cur: 12. Board id: 0. not match..skip..
All ddr config failed...
Reset...
boot times 0SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:0;READ:0;0.0;CHK:0;
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0001 - pwm id 0x00
bl2_stage_init 0xc0
bl2_stage_init 0x02

L0:00000000
L1:00000703
L2:00008067
L3:15000020
S1:00000000
B2:20282000
B1:a0f83180

TE: 135021

BL2 Built : 14:57:11, Sep  1 2020. g12a g3c95fed - gongwei.chen@droid11-sz

Board ID = 1
Set cpu clk to 24M
Set clk81 to 24M
Use GP1_pll as DSU clk.
DSU clk: 1200 Mhz
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
board id: 1
Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
PIEI prepare done
00000000
emmc switch 1 ok
ddr saved addr:00016000
Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
00000000
emmc switch 0 ok
fastboot data verify
result: 255
Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
DDR4 probe

LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep  1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
ddr clk to 1320MHz

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 3. Board id: 255. Force loop cfg
DDR3 probe
ddr clk to 648MHz

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 4. Board id: 255. Force loop cfg
DDR3 probe
ddr clk to 648MHz

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 5. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 912MHz

dmc_version 0001
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : End of initialization
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 6. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 912MHz

dmc_version 0001
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : End of initialization
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 7. Board id: 0. not match..skip..
Cfg max: 12, cur: 8. Board id: 0. not match..skip..
Cfg max: 12, cur: 9. Board id: 0. not match..skip..
Cfg max: 12, cur: 10. Board id: 0. not match..skip..
Cfg max: 12, cur: 11. Board id: 0. not match..skip..
Cfg max: 12, cur: 12. Board id: 0. not match..skip..
All ddr config failed...
Reset...
boot times 0
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em3ka
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#2

https://forum.khadas.com/t/vim3l-booloa ... error/6240
masteripper wrote: Wed Jun 23, 2021 8:41 am Is UART flashing a good option...has someone done it successfully ?
Yes, try first with NAND Mask ROM mode...
masteripper
Posts: 3
Joined: Wed Jun 23, 2021 8:33 am
Has thanked: 1 time

#3

The problem is that i can't find the short pins
I have the Samsung KLMCG2KETM-B041 eMMC....only 8 pins if i remember correctly ... and haven't found anything on the net
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em3ka
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#4

masteripper wrote: Wed Jun 23, 2021 9:24 am The problem is that i can't find the short pins...
02.jpg
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masteripper
Posts: 3
Joined: Wed Jun 23, 2021 8:33 am
Has thanked: 1 time

#5

em3ka wrote: Wed Jun 23, 2021 10:22 am
masteripper wrote: Wed Jun 23, 2021 9:24 am The problem is that i can't find the short pins...
Thanks a lot my friend....I will try asap...thanks
The procedure is :
Have the usb OTG cable connected....power on and briefly short circuit the 2 pins.. ?
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